We present an approach to aid in debugging/development of scheduling algorithm implementations. Our technique makes use of
a sequence of a correctness-preserving RTL transformation called Register Transfer Split (RTS), to collectively perform the same task as that of a scheduler. Violation of the transformation precondition signals an error
and the sequence of RTS transformations applied so far forms a trace which can be used for debugging purposes.
This work was sponsored by DARPA, monitored by US Army Ft. Huachuca under contract number DABT63-96-C-0051 and NSF (grant
number 9634462).