High-end applications have been designed for the MORPHEUS computing platform to fully demonstrate its potential as a high-performance reconfigurable architecture. These applications are characterized by demanding memory bandwidth requirements, as well as multiple processing stages that necessitate dynamic reconfiguration of the heterogeneous processing engines. Two hardware services have been specifically designed to meet these requirements. This Chapter first describes the unit responsible for reconfiguration of the various processing engines presented in Chapters 4–6 and the predictive method used to hide reconfiguration latencies. The second part of this Chapter describes a bandwidth-optimized DDR-SDRAM memory controller, which has been designed for the MORPHEUS platform and its Network On Chip interconnect in order to meet massive memory throughput requirements and to eliminate external memory bottlenecks.